During ESD, large currents may flow through an integrated circuit (IC), which can potentially cause damage to the IC. Damage can occur within a device included in the IC that conducts the current, as well as in devices that are exposed to a significant voltage drop across them due to the large current flow. To avoid damage due to an ESD event, clamps are added the IC design. These clamps shunt the large ESD current without causing high voltage over sensitive nodes of the IC.
Many conventional ESD clamps suffer from being too slow to trigger. In conventional ESD clamps, the time between the IC being exposed to the ESD event and triggering of the clamp is too long, such that the voltage over a node to be protected can exceed the maximum tolerated voltage for this node. The peak voltage experienced by the protected node during the reaction time of the ESD clamp is called the voltage overshoot. Device failures result from exposure to the maximum voltage allowed by a slow reaction time of the clamp.
A silicon controlled rectifier (SCR) is an example of a conventional clamp used for ESD protection. Conventional SCRs are known to have a high trigger voltage and a slow reaction time, making them seemingly impractical for ESD protection in advanced process nodes.
The high trigger voltage of the conventional SCR has been overcome by triggering the conventional SCR through either the G1 trigger gate, the G2 trigger gate, or both trigger gates of the conventional SCR. A trigger circuit applied to these nodes can be tuned to trigger at a desired voltage level.
For fast ESD events such as CDM events, the reaction time of conventional SCRs may be too slow. Therefore, there is a need to speed up the triggering of the conventional SCR. Hereinafter is disclosed embodiments of a ESD protection circuits with reduced SCR reaction time and thereby reduced voltage overshoot.